Protecting the connection
between quantum computers.

Connecting quantum computers gives us a way to build larger machines from smaller pieces. It also gives quantum information another place to get into trouble: the connection itself.

Operations between quantum processing units, or QPUs, can be much noisier than operations inside one processor. That makes the boundary an especially interesting place to think about quantum error correction. If the noise is uneven, how should we distribute the protection?

That question is at the heart of our new preprint, Error Suppression in Distributed Quantum Computing with Heterogeneous-Distance Lattice Surgery, now on arXiv.

A bigger helper at the boundary

In the surface code, a logical qubit is encoded in a patch of physical qubits. Repeated checks help us detect errors without reading out the quantum information we want to preserve. The code distance, written d, is the fewest physical-qubit errors that can change the encoded information without being caught by the checks. With sufficiently low physical noise and suitable error-correction circuits, increasing the distance strengthens protection, but requires more qubits.

Making every patch larger is one way to protect a distributed computation. Our approach keeps the data patches compact and enlarges a helper patch, called an ancilla, that spans the boundary between processors. The data patches stay at distance d; the central ancilla has distance 2d + 1.

The resulting architecture is called 8-DAM, short for eight-data-patch ancilla-mediated. The name refers to eight possible neighboring data-patch positions around the central ancilla. The boundary runs through that ancilla, so the noisier operations between processors occur inside the enlarged helper patch.

EXPLORE THE ARCHITECTURE

Where should the extra protection go?

Compare three allocation strategies and watch which patches grow.

The checks matter, too

Lattice surgery lets encoded qubits interact by temporarily merging and splitting code patches to measure joint properties. Here, those operations connect patches of different sizes.

That changes the geometry of possible logical errors. During error checking, one fault can spread to multiple data qubits, producing correlated errors known as hook errors. The order of the checking gates matters because it can let those errors line up along a logical error path.

We adapt a technique called traveling stabilizers to these unequal-size patches. The checks shift as the circuit progresses; the physical qubits stay put. The scheduling helps prevent hook errors from undermining the intended protection during the merge and split operations. Our results evaluate this schedule together with the larger ancilla.

What the simulations show

We study a logical controlled-NOT (CNOT), a basic operation between two encoded qubits. We tested the circuits with a local depolarizing-noise parameter of 0.01%, while varying the link parameter from 0.1% to 1%: ten to one hundred times larger. The quantities we measured were logical-readout failure probabilities for selected observables over a complete circuit.

At the highest tested link noise, the 3–7–3 construction — distance-3 control and target patches with a distance-7 ancilla — gave approximately 13 and 19 times lower control-X and target-Z readout-failure probabilities, respectively, than uniform distance-3 circuits. The mixed-distance results also varied much less as link noise increased. See the single-CNOT results.

We also extend the shared-ancilla design to two simultaneous distributed logical CNOTs between four data qubits. In the target-Z readout simulations, it shows weaker dependence on link noise than two independent uniform distance-3 CNOTs. See the dual-CNOT results.

The tradeoff is part of the result

The smaller footprint comes with more repeated use of the connection. The 5–11–5 circuit needs fewer distinct inter-QPU coupling pairs than uniform distance-9 — 11 versus 17 — but executes 264 inter-QPU CNOTs rather than 153 over the full circuit. Whether that is a useful exchange depends on the hardware, including how much time each link operation takes.

These are circuit simulations of selected readout errors, not a measurement of total logical-gate failure probability or a hardware demonstration. The model leaves out idle noise, link-generation failures and latency, leakage, and correlated link faults. Testing those effects is an important next step.

What I find compelling about this direction is the design question it opens up: how much can we gain by putting additional protection exactly where an architecture needs it? For a modular quantum computer with a limited qubit budget, the placement of error correction can matter as much as its size.